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Events categorized as (Public Events)

• 22
  Jan

  PHD-EE THESIS DEFENSE "A FRAMEWORK FOR BATTERY PACK HYGIENE IN ELECTRIC VEHICLES: ENHANCING LITHIUM-ION BATTERY LIFE THROUGH STRATEGIC SOC MANAGEMENT AND DIAGNOSTIC ANALYSIS"

  Date: January 22, 2026
  Time: 03:00 PM
  Location: EE Reading Room and online via zoom

  Speaker: Ayesha Khan
  Supervisor: Dr. Ijaz Haider Naqvi
  

  Join Zoom Meeting: Join Zoom Meeting https://lums-edu-pk.zoom.us/j/92620596965?pwd=aaqL6hTrHfRdQ4hhA2GWNH5XHt0GS0.1 Global climate change has prompted policies to reduce greenhouse gas emissions, with transportation electrification offering a pathway to lower noise and pollutant levels and improve urban quality of life. As electric mobility expands, lithium-ion batteries (LIBs) remain central to sustainable transportation. However, their high cost and gradual capacity degradation continue to limit the large-scale adoption of battery electric vehicles (BEVs), especially in regions with diverse terrains where frequent battery replacement reduces long-term viability. Minimizing degradation and extending battery pack lifespan is therefore a critical challenge. This research investigates strategies to improve what we refer to as battery pack hygiene—a structured set of operational and diagnostic practices aimed at slowing degradation and sustaining battery performance over time. A key focus is on managing the state of charge (SoC) in BEVs and understanding how different driving profiles influence battery health. Real-world driving patterns impose varying electrochemical and thermal stresses, and this study develops a modeling framework to examine how SoC policies shape degradation behavior across diverse profiles. The thesis examines the topic from multiple angles, including region-specific driving behavior and the impact of different charging levels on battery health degradation. The work also analyzes the trade-offs among performance metrics such as degradation rate, driving range, charging duration, and aging cost, identifying operational regimes that achieve a practical balance across competing objectives. This thesis also highlights the influence of cycling policies—particularly charging rate—on degradation mechanisms and their correlation with capacity fade. While ICA/DVA and EIS provide complementary insights into capacity loss and impedance growth, further refinement is needed to improve their quantitative accuracy. To support the simulation-based analysis, publicly available aging datasets from the Stanford Energy Control Laboratory are used, where cells were cycled under the UDDS profile at C/2 and 3C charging rates. A mechanistic diagnostic approach combining Incremental Capacity/Differential Voltage (ICA/DVA) and Electrochemical Impedance Spectroscopy (EIS) is applied to quantify three key degradation modes: loss of lithium inventory (LLI), loss of active material (LAM), and loss of conductivity (LC). Together, these contributions define a structured approach to Battery Pack Hygiene, supporting the development of electric vehicles whose batteries degrade more slowly, operate more efficiently, and remain economically viable over longer lifetimes.

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• 23
  Jan

  EE FACULTY CANDIDACY TALK "FROM EEG BIOMARKERS TO SILICON: ULTRA-LOW-POWER INFERENCE PROCESSORS FOR BIOMEDICAL APPLICATIONS."

  Date: January 23, 2026
  Time: 11:00 AM
  Location: EE Reading Room

  Speaker: Dr. Abdul Rehman Aslam
  

  Emotion dysregulation and negative affectivity are among the most challenging behavioral traits associated with Autism Spectrum Disorder (ASD), yet existing diagnostic and assistive solutions rely heavily on software-based analysis that is power-hungry, latency-prone, and unsuitable for continuous real-time deployment. This seminar presents the design and validation of an ultra-low-power on-chip processor for emotion-aware assistance in individuals with ASD, using electroencephalography (EEG) signals as the primary sensing modality. The talk will cover the complete end-to-end hardware–algorithm co-design methodology, starting from large-scale EEG feature extraction and biomarker identification, followed by the development of patient-specific machine learning models optimized for hardware implementation. A custom neural-network–based inference architecture is then mapped onto a dedicated System-on-Chip (SoC), designed and taped-out in CMOS technology, achieving microjoule-level energy consumption per classification while maintaining clinically relevant accuracy. Key contributions include feature-aware hardware optimization, channel-efficient EEG processing, and a deeply pipelined low-power inference engine validated through FPGA prototyping and post-layout analysis. Building upon this foundation, the final part of the seminar will outline a future research vision centered on reconfigurable and scalable inference accelerators for long-term biomedical monitoring and next-generation embedded intelligence. This includes extending the presented architecture toward multi-modal physiological sensing, adaptive on-chip learning, and technology scaling to advanced nodes for further energy reduction. The vision also encompasses close integration of algorithmic robustness, circuit-level innovation, and system-level validation, enabling practical deployment in wearable and edge devices. Through this direction, the research aims to bridge fundamental VLSI design with real-world healthcare and embedded AI applications, while fostering interdisciplinary collaboration and externally funded research programs.

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